This invention relates to electronic processing circuits and devices and more particularly to methods and devices for controlling data transfers between such circuits and devices.
Many electronic devices have processors that communicate with one or more external memory devices, such as hard disk drives, read-only memory cards, and flash memory cards. Today, flash memory accesses are controlled by a flash memory interface controller that is connected to a device's host processor via a system bus.
FIG. 1 is a block diagram of a processing system 100 that includes a typical arrangement for controlling flash memory accesses. In pertinent part, the system 100 includes a host processor 102 and an interface controller 104, and possibly various other devices 106, 108, 110, all of which communicate through a system bus 112. The interface controller 104 is in charge of transferring data to and from a flash memory device 114 using control and data bus signals that typically conform to widely followed standard practices in the flash memory industry. Besides exchanging data with the device 114, the controller 104 sends control signals to the device 114 and receives ready/busy signals from the device 114.
After each “page write”, it is common for the memory device 114 to be queried by the host processor 102 in order to determine if the write operation was successful. The particular format of the command and contents of the response are set by the manufacturer of the memory device 114, but many manufacturers adhere to a de facto industry standard that specifies that the “read status” command is “0x70h” and that any response other than “0x00h” indicates an error. It will be understood that the command and response is written in hexadecimal notation, where x indicates a don't-care character.
One arrangement of such an interface controller is described in U.S. Pat. No. 5,457,787 to Asano et al., which states that it describes an interface circuit for a peripheral device that generates an interrupt request to a host in response to a data request from the peripheral device and drops the interrupt request if the status of the peripheral device is read by the host. The interface circuit detects that the host operates in a post-read mode, and responds to a post-read mode detect signal and the status reading by the host in order to enable the regeneration of the interrupt request to the host.
U.S. Pat. No. 6,249,461 to Choi et al., for example, describes a flash memory device that provides a “status read” operation for indicating its status of operation.
After each “page write” operation, the memory device is usually queried “read status” in order to determine if the write operation was successful. This is done by the host processor's issuing a standard “read status” command and then reading the response returned by the memory device. The usual “read status” operation is performed immediately after a flash memory device transfers a page of data from its internal buffer into its storage array. The end of this transfer is marked by the flash memory device's ready/busy signal output being de-asserted. The host processor detects the de-assertion and then issues the “read status” command.
A problem arises from the host processor's having to check every “read status” response. The host processor has to stop other system operations in order to issue a “read status” command, read the response, and upon encountering an error (which is usually rare) act accordingly. This degrades overall system performance, perhaps dramatically because the host processor may have to be diverted to service memory “read status” operations almost continuously. From another point of view, the problem is the excessive bandwidth required by the host processor to query the memory device status following a “page write” operation.
U.S. Pat. No. 5,640,349 to Kakinuma et al. describes a flash memory card having two flash memories and a flash memory controller having a pair of buffer memories and a pair of data busses. Because the data busses can operate in parallel, the transfer time between the host and the flash memory card is reduced. It does not describe either detecting a programmable bit sequence sent to the flash memory indicating whether a response will need to be read or tracking memory accesses (address and data in a multi-buffered queue scheme) that result in errors.
U.S. Pat. No. 6,985,778 to Kim et al. describes an interface between a host processor and a NAND flash memory, which includes a register that receives and stores a command from the host processor to control an operation of the NAND flash memory and an operation information to execute the command. A flash interface portion, also in the memory, controls a control signal to operate the NAND flash memory; outputs the command, the operation information, or the host data; and controls an input/output connection through which the data is input to the NAND flash memory. It does not describe either detecting a programmable bit sequence sent to the flash memory indicating whether a response will need to be read or tracking memory accesses (address and data in a multi-buffered queue scheme) that result in errors.
U.S. Pat. No. 5,799,168 to Ban describes a flash memory controller that translates generic commands from a processor into memory-circuit-specific commands, and vice versa. After writing or erasing, the controller automatically enters a “read status”, and the controller can extract read-status information through pre-determined registers and software polling. It does not describe either detecting a programmable bit sequence sent to the flash memory indicating whether a response will need to be read or issuing an interrupt request upon encountering an error response.